This year marks the 27th anniversary of IBM’s CMOS/Cu BEOL [Back End of the (manufacturing) Line] on-chip interconnect technology reaching production, with the first high-end Cu CPU chips passing manufacturing qualification and being sampled to customers. This announcement shocked the industry, who were unaware that Cu had been taken beyond the early research phase. Our original definition of Cu BEOL materials, processes, “dual damascene” integration scheme, and multilevel “hierarchical” architecture has stood the test of time, thanks to the robustness of this definition, plus continuous, small incremental innovations to combat the negative scaling trends for micro- and nano-scale metal wires (as opposed to transistors). Now entering its 14th generation of manufacturing, and 16th in R&D, our minimum-width 2 nm CMOS node Cu wires have been scaled by 1/40x from first inception, to just above 10 nm.
This talk covers the Cu BEOL innovation timeline, from defining elements through our most recent breakthroughs. With the latest innovations, we challenge the oft-heard predictions of the end of the roadmap for Cu and damascene integration. This puts us in position to provide unique pointers to further Cu extendibility, and further damascene extendibility for conductors beyond Cu.For example, I’ll show preliminary data on a best-choice post-Cu metal, and comment on our joint research with RPI on sub-dimensional novel conductors. Again in contrast to current industry roadmaps calling for a reversal to the erstwhile subtractively-etched wiring integration scheme, I suggest there is potential to continue with the standard, manufacturable damascene process.
Dr. Edelstein is an IBM Fellow, and Chief Interconnect Strategist in Semiconductor Technology Research and Development organization. He received his B.S., M.S., and Ph.D. degrees in Applied Physics from Cornell Universityin ultrafast quantum electronics. At IBM, he has worked for 35 years on nearly all aspects of Cu- and Cu/Low-k ULSI multilevel on-chip interconnect technologies, along with associated device integration, for high-performance microelectronics products. He led teams for IBM’s industry-first “Cu Chip” technology in 1997, Cu/Low-k (SiCOH) insulation in 2004, and Cu/airgap technology in 2007. He has led other interconnect-related projects in 3D integration, Quantum Computing, Magnetic Random Access Memory (MRAM) product integration, and currently leading-edge Cu extendibility for the 2 nm node and beyond.
He currently holds 310 U.S. patents, and has received various IBM technical, patent, and corporate awards. He shared honors for “Inventor of the Year 2006” by the NY State IP Law Assoc., and for IBM’s 2004 National Medal of Technology for 40 years of semiconductor innovations. He was appointed IBM Fellow in 2006, and elected to the National Academy of Engineering in 2011, both for his seminal contributions to Cu-based ULSI interconnect technologies.