Materials are at the heart of everything in the semiconductor industry, from the cell phones in our pockets to the mainframes powering global financial transactions. This talk will highlight some of the key challenges and opportunities for materials engineering in leading-edge semiconductor architectures. State-of-the-art interconnects can be fabricated with atomic-level precision to co-optimize electrical performance and reliability. First-principles-based simulation can help us identify promising candidate materials for next-generation interconnect wiring. Dielectrics with embedded air gaps can be engineered to reduce parasitic capacitance in both back- end-of-line interconnect wiring and front-end-of-line transistors. Small materials changes at the nano-scale can translate to chip-level performance improvement in leading-edge semiconductor technologies.
Nick Lanzillo earned a B.S. in physics from Syracuse University in 2009 followed by a Ph.D. in physics from RPI in 2014. After a brief stint in academia, he joined IBM Research in 2016 as part of the interconnect integration team based in Albany, NY. Over the past decade, Nick has worked on architecture definition and performance benchmarking for leading-edge semiconductor technologies. His current research focuses on interconnect scalability, advanced transistor architectures, design- technology co-optimization and quantum computing. Nick has authored or co-authored more than 80 publications and conference papers and holds more than 100 granted US patents.